Title :
Static Frequency Divider with Enhanced Frequency Performance
Author :
Upadhyaya, Prasanna ; La Rue, George S.
Author_Institution :
Washington State Univ., Pullman, WA
Abstract :
This paper presents the design and measured results of a novel static frequency divider that operates at a frequency 28% higher than a current-mode logic (CML) divider. The frequency divider was designed and implemented in IBM´s 0.5 mum SiGe BiCMOS technology with an fT of 47 GHz. The divider adds an additional delayed clock phase to a conventional CML- based divider. Measured results show operation up to 26 GHz with power dissipation of 59 mW compared to a CML divider that operates up to 20.4 GHz with power dissipation of 54.6 mW.
Keywords :
BiCMOS integrated circuits; current-mode logic; frequency dividers; BiCMOS technology; SiGe; current mode logic; delayed clock phase; enhanced frequency performance; frequency 26 GHz; power 59 mW; static frequency divider; Added delay; BiCMOS integrated circuits; Clocks; Current measurement; Frequency conversion; Frequency measurement; Germanium silicon alloys; Logic design; Power dissipation; Silicon germanium; Current mode logic; high-speed; static frequency divider;
Conference_Titel :
Microelectronics and Electron Devices, 2008. WMED 2008. IEEE Workshop on
Conference_Location :
Boise, ID
Print_ISBN :
978-1-4244-2343-9
Electronic_ISBN :
978-1-4244-2344-6
DOI :
10.1109/WMED.2008.4510658
