Delay and energy efficient data transmission for on-chip buses

On-chip buses in deep sub-micron designs consume significant amounts of power and have large propagation delays. Thus, minimizing power consumption and propagation delay are the most important design objectives. In this paper, we propose a technique for delay and energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by focusing on the LI cache address/data buses of a microprocessor using the SPEC2000 CINT benchmark suit. We show that our technique achieves 31% (30%) of delay improvement along with energy savings of 13% (9%) over the base case for data transmission on address (data) bus