A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers

Author

Wang, Yan ; Lee, Kyehyung ; Temes, Gabor C.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR

fYear

2008

fDate

21-24 Sept. 2008

Firstpage

97

Lastpage

100

Abstract

A new dynamically-biased scheme is proposed to implement a 13-bit delta-sigma modulator with a 2.5 MHz signal bandwidth. It uses the low-distortion architecture, and hence the opamp linearity requirements are greatly relaxed. Its noise-coupled and time-interleaved structure further decreases the power consumption. The prototype chip was fabricated in a 0.18 um CMOS technology. Experimental results show that 78 dB SNDR is achieved when it is clocked at 60 MHz sampling rate. With 1.6 V power supply, the power dissipation is 19.2 mW.

Keywords

CMOS integrated circuits; delta-sigma modulation; operational amplifiers; CMOS technology; bandwidth 2.5 MHz; delta-sigma modulator; dynamically biased amplifiers; frequency 60 MHz; low-distortion architecture; opamp linearity requirements; Bandwidth; CMOS technology; Clocks; Delta modulation; Energy consumption; Linearity; Power dissipation; Power supplies; Prototypes; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-2018-6

Electronic_ISBN

978-1-4244-2019-3

Type

conf

DOI

10.1109/CICC.2008.4672030

Filename

4672030