Clock gated static pulsed flip-flop (CGSPFF) in sub 100 nm technology

In this paper, a new flip flop called clock gated static pulsed flip-flop (CGSPFF) is proposed. The dynamic power consumption in CGSPFF is reduced by avoiding unnecessary input pulse transitions with clock gating. Two transistors in the main block of the flip-flop are eliminated to achieve low leakage power as well. Using the new clock pulse generator leads to a higher operational speed and lower power consumption compared to the previously proposed flip-flops. The results of the simulation show that the PDP of the proposed flip flop is reduced by at least 58.3%.