A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiers

A 15 b power-efficient pipeline A/D converter using capacitance-coupling non-slewing amplifiers is presented. A modified 1.5b/stage transfer curve combined with the non-slewing amplifier is useful for the error corrections of incomplete settling error. The relationship between the input signal and the incomplete settling errors can be linearized and the errors can be corrected in digital domain with a simple calculation. A prototype ADC fabricated in 0.25 mum process consumes 123 mW at 30 MSample/s and 2.5 V power supply. The SNDR and the SFDR at 30 MS/s are 75.0 dB and 86.5 dB, respectively with the incomplete settling error corrections.