Multi-level buffer block planning and buffer insertion for large design circuits

Buffer insertion plays an increasingly critical role on circuit performance and signal integrity, especially in deep submicron region. Buffer insertion stage is very important for buffering efficiency. Early buffer insertion (e.g. at the floorplanning stage) may cause misestimation due to unknown cell locations, on the other hand buffer insertion after placement or during global routing may tend to be ineffective because the cell locations have been fixed and buffer resources may be distributed inappropriately. In this paper, a new method for buffer insertion is presented which inserts buffers during placement based on the planning of buffers at the floorplanning stage and congestion considerations. Experiments show that by our method, performance and congestion control are improved in large circuits including large amount of buffers