DocumentCode :
3359288
Title :
Recognition of Sensitized Longest Paths in Transition Delay Test
Author :
Hamada, Shuji ; Maeda, Toshiyuki ; Takatori, Atsuo ; Noduyama, Yasuyuki ; Sato, Yasuo
Author_Institution :
Semicond. Technol. Acad. Res. Center, Yokohama
fYear :
2006
fDate :
Oct. 2006
Firstpage :
1
Lastpage :
6
Abstract :
The progress of design and fabrication technologies has led to an increase in small delay failures in systems-on-a-chip. To evaluate the delay testing quality accurately, the authors have already proposed a statistical approach that calculates actual sensitized path lengths that detect small delay defects in the transition delay test. However, the calculation requires a huge amount of CPU time. This paper presents a much more efficient method to calculate the sensitized longest path lengths and experimental results regarding CPU time and accuracy. The experiments show that this calculation method has high speed and high accuracy
Keywords :
automatic test pattern generation; delays; statistical analysis; system-on-chip; CPU accuracy; CPU time; delay failures; delay testing quality; sensitized longest path lengths; statistical analysis; systems-on-a-chip; transition delay test; Automatic test pattern generation; Clocks; Delay estimation; Delay systems; Design for testability; Fabrication; Probability; Semiconductor device testing; System testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
ISSN :
1089-3539
Print_ISBN :
1-4244-0292-1
Electronic_ISBN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2006.297622
Filename :
4079300
Link To Document :
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