Title :
Effect of glitches on the efficiency of components´ region-constrained placement as a fast approach to reduce FPGA´s dynamic power consumption
Author :
Esmaeili, S.E. ; Khachab, N.I. ; Ghannam, M.Y.
Author_Institution :
EE Dept., Kuwait Univ., Safat
Abstract :
The effect of components´ region-constrained placement on reducing internal nets total capacitance and the corresponding change in internal nets´ total dynamic power consumption is investigated. Two logic circuits were specified as components covering around 80% of total FPGA busy gates. These components are multiplexers and adders along with multipliers. Each of these components was implemented on two of Xilinx FPGA´s families, namely; Spartan II and Virtex. Gate-level power estimation for different region-constrained placements of each logic circuit was carried out using the Xilinx hierarchal power distribution analyzer, XFower
Keywords :
adders; circuit layout; field programmable gate arrays; logic design; logic gates; multiplying circuits; FPGA gates; Spartan II; Virtex; XFower power distribution analyzer; Xilinx FPGA; adders; dynamic power consumption reduction; gate-level power estimation; glitch effect; internal net total capacitance; logic circuits; multiplexers; multipliers; region-constrained placement; Adders; Arithmetic; Capacitance; Delay; Energy consumption; Logic circuits; Multiplexing; Power dissipation; Signal design; Very large scale integration;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.39
