Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI’s

A teacher-student swap (TSS) test method with the dual supply voltage (V_DD) for the ultra low V_DD homogeneous multi-core LSIpsilas is proposed and the test chips are fabricated in 90 nm CMOS. In this method, two same cores with different power supply voltages test each other by comparing their outputs, which eliminates the need for the expected vector. When V_DD is less than 0.3 V, the die-to-die power reduction by the dual V_DD in the 5 chips was from 18% to 48%. In order to manage the large die-to-die variations at low V_DD, the fine grain dual V_DD with TSS test method is a promising approach without increasing the test cost.