Comparison of Delay Tests on Silicon

Testing longer paths in an integrated circuit with a proper path selection strategy has the potential to increase the quality of a delay test. However, the benefit on silicon is not completely clear because a theoretical test quality increase is normally simulated using an assumed distribution of defect sizes. In this work, silicon data is collected and maximum operating frequency (Fmax) compared using test patterns generated by a variety of delay test methodologies. The silicon data is consistent with theoretical predictions and the benefits of testing delay faults through the longest path are quantified