Spurs modeling in direct digital period synthesizers related to phase accumulator truncation

This paper presents an analytic model of the spurious noise frequencies in direct digital period synthesizer (DDPS) due to phase accumulation truncation. DDPS is a new technique for frequency synthesis that takes advantage of the speed and low jitter of a delay-locked-loop-based frequency multipliers and the ability to digitally control the frequency from the direct digital synthesis technique DDS according to Calbaza and Savaria (2000) and Calbaza and Savaria (2002). The most important source of spurious noise frequencies in a DDPS circuit is the truncation of the output of its phase accumulator. Computing spectral analysis of DDPS circuit is a CPU time consuming task. Based on series of analytic calculations, a general and simple mathematical formula of the location of spurious frequencies and their magnitudes is predicted. This formula will help designers analyze and develop new DDPS circuits faster.