DocumentCode
3359356
Title
A regular layout approach for ASICs
Author
Menezes, C. ; Meinhard, C. ; Reis, R. ; Tavares, R.
Author_Institution
Instituto de Informatica, UFRGS, Brazil
fYear
2006
fDate
2-3 March 2006
Abstract
This paper presents a regular layout approach addressing the need of a more predictable circuit performance and DFM. Experiments were done using a regular matrix of cells composed by 2-input NAND gates. The regular layout approach considers some strategies to improve the predictability of connections and the routability of circuits. Initial experiments show that this approach should improve performance when compared with a standard cell approach.
Keywords
application specific integrated circuits; integrated circuit layout; logic design; logic gates; network routing; 2-input NAND gates; ASIC; DFM; cell regular matrix; circuit routability; connection predictability; regular layout approach; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Circuit optimization; Circuit synthesis; Delay estimation; Design for manufacture; Inverters; Routing; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location
Karlsruhe
Print_ISBN
0-7695-2533-4
Type
conf
DOI
10.1109/ISVLSI.2006.11
Filename
1602478
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