Testing of Precision DACs Using Low-Resolution ADCs with Dithering

The bottleneck of DAC testing is the fast and accurate measurement devices. Production testing of high-resolution DACs with gigahertz clock rates is a challenging problem, and there is no widely adopted approach for on-chip testing of precision DACs in an SoC system. This work presents a new approach for testing high-resolution DACs. High speed data acquisition is achieved with flash ADCs; sufficient resolution is provided by dithering; and high test accuracy is guaranteed by the proposed data processing algorithm. This method provides a potential solution to both the production and on-chip DAC testing problems. Simulation results show that the static linearity of 14 bit DACs can be tested to better than 1 LSB accuracy, and dynamic performance of more than 85 dB SFDR can be tested with 1 dB accuracy, using 6-bit ADCs and dithering. Experimental results included in the paper also affirm the performance of the algorithm in testing high-resolution DACs using 6-bit ADCs