Title :
Dual-mode high-speed low-energy binary addition
Author :
Grad, J. ; Stine, J.E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
Abstract :
Sparse tree adders are a common choice for the implementation of high performance binary addition. However, for constant supply voltage they have constant energy consumption regardless of the operating frequency. This paper presents a dual-mode sparse tree adder that offers a low-speed low-energy mode. This is achieved by disabling the prefix tree in the low-speed mode. Simulation results using extracted mask layouts show a reduction in energy consumption in the low-speed mode by a factor of 3.6 in static CMOS and a factor of 2.3 in domino logic
Keywords :
CMOS digital integrated circuits; adders; digital arithmetic; formal logic; high-speed integrated circuits; low-power electronics; trees (mathematics); domino logic; dual-mode binary addition; dual-mode sparse tree adder; energy consumption; high-speed binary addition; low-energy binary addition; low-energy mode; low-speed mode; mask layouts; static CMOS; Adders; CMOS logic circuits; Capacitance; Clocks; Energy consumption; Frequency; High performance computing; Power engineering and energy; Propagation delay; Voltage;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.37
