• DocumentCode
    3359407
  • Title

    FlexCore: Implementing an exposed datapath processor

  • Author

    Sjalander, M. ; Larsson-Edefors, Per

  • Author_Institution
    Comput. Sci. Dept., Florida State Univ., Tallahassee, FL, USA
  • fYear
    2013
  • fDate
    15-18 July 2013
  • Firstpage
    306
  • Lastpage
    313
  • Abstract
    The FlexCore processor is the resulting implementation of an exposed datapath approach conceptualized in the FlexSoC programme. By way of a crossbar switch interconnect, all execution units in a FlexCore datapath can potentially communicate, allowing the inherent hardware parallelism to be utilized. This interconnect enables configuration of a datapath to match an application domain, for example, by way of datapath accelerators. The baseline FlexCore is a general-purpose processor (GPP) and since all FlexCore configurations are extensions to the baseline, they offer GPP functionality as complement to the domain-specific functionality. This paper gives an overview of the implementation of complete FlexCore processors, accompanied with discussions on datapath interconnects, datapath extensions and instruction decompression.
  • Keywords
    multiprocessor interconnection networks; parallel architectures; FlexCore configurations; FlexCore processors; FlexSoC programme; GPP functionality; crossbar switch interconnect; data-path accelerators; datapath extensions; datapath processor; general-purpose processor; hardware parallelism; instruction decompression; Benchmark testing; Field programmable gate arrays; Hardware; Ports (Computers); Radio frequency; Registers; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013 International Conference on
  • Conference_Location
    Agios Konstantinos
  • Type

    conf

  • DOI
    10.1109/SAMOS.2013.6621139
  • Filename
    6621139