Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz

A digital technique for the compensation of dynamic nonlinearities at the front-end of high-speed, high-resolution ADCs is presented. The complexity of the digital post-processing scheme is minimized using judicious modeling of the relevant nonidealities. Applying the method to a 14-bit, 155-MS/s ADC provides > 83 dB SFDR up to f_in = 470 MHz. The post-processing block is estimated to consume 52 mW and occupy 0.54 mm² in 90-nm CMOS.