Title :
Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementation
Author :
Berthelot, F. ; Nouvel, F.
Author_Institution :
CNRS UMR 6164, IETR-INSA, Rennes
Abstract :
Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level adequation algorithm architecture process. We present a method generates automatically the design for both partially and fixed parts of FPGAs
Keywords :
field programmable gate arrays; reconfigurable architectures; FPGA fixed parts; dynamic reconfiguration; high level adequation algorithm; partial reconfiguration; top down design methodology; Design methodology; Digital signal processors; Field programmable gate arrays; Hardware; Multimedia systems; Runtime; Signal processing algorithms; Software performance; Software radio; Switches;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.71
