Title :
SiP-TAP: JTAG for SiP
Author :
De Jong, Franciska ; Biewenga, Alex
Author_Institution :
Philips Res., Eindhoven
Abstract :
The IEEE Std. 1149.1-2001 (1149.1) solution for test poses a challenge when used for system-in-a- package (SiP). Like a multi chip module (MCM), a SiP adds a hierarchy layer to a board design in a similar way as a daughter board does. However, when a customer views a SiP as an IC, it is not conform to the IEEE 1149.1 standard. This paper discusses this discrepancy from a vendor and a customer perspective and presents a solution. The implementation is low cost and can be a general addition to the test access port (TAP) of all dies using 1149.1. The effects on test preparation, BSDL file impact, software flow and the actual use are discussed as well
Keywords :
IEEE standards; integrated circuit testing; system-in-package; BSDL file impact; IEEE Std. 1149.1-2001; JTAG; SiP-TAP; software flow; system-in-a-package; test access port; Assembly; Costs; Debugging; Digital integrated circuits; Integrated circuit testing; Packaging; Performance evaluation; Pins; Production; System testing;
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
1-4244-0292-1
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2006.297633
