Power Supply Noise in Delay Testing

Author

Wang, Jing ; Walker, D.M.H. ; Majhi, Ananta ; Kruseman, Bram ; Gronthoud, Guido ; Villagra, Luis Elvira ; van de Wiel, P. ; Eichenberger, Stefan

Author_Institution

Dept. of Comput. Sci., Texas A&M Univ., College Station, TX

fYear

2006

fDate

Oct. 2006

Firstpage

1

Lastpage

10

Abstract

Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don´t care fill approaches. The power supply noise impact on delay must be taken into account when delay tests are applied

Keywords

delays; integrated circuit noise; integrated circuit packaging; integrated circuit testing; lead bonding; power supply circuits; silicon; timing; Si; array-bond chips; delay testing; don´t care fill approaches; low-cost noise models; noise analysis methodology; power supply noise analysis; timing analysis; wire-bond chips; CMOS technology; Circuit faults; Circuit noise; Circuit testing; Crosstalk; Delay; Noise level; Power supplies; Semiconductor device noise; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2006. ITC '06. IEEE International

Conference_Location

Santa Clara, CA

ISSN

1089-3539

Print_ISBN

1-4244-0292-1

Electronic_ISBN

1089-3539

Type

conf

DOI

10.1109/TEST.2006.297642

Filename

4079320