Title :
A VLSI GFP frame delineation circuit
Author :
Toal, C. ; Sezer, S. ; Xin Yang
Author_Institution :
Inst. of Commun. & Inf. Technol., Queen Univ., Belfast, UK
Abstract :
This paper presents the design and study of circuit architecture able to perform 16 Gbps GFP frame delineation with single bit error correction using UMC 130 nm standard cell technology. The design targets the development of a hard macro core for the design of next generation network processing platforms.
Keywords :
VLSI; error correction; integrated circuit design; 130 nm; 16 Gbit/s; UMC technology; VLSI GFP frame delineation circuit; bit error correction; circuit architecture; hard macro core; Circuit synthesis; Computer buffers; Cyclic redundancy check; Error correction; Information technology; Payloads; Polynomials; Read only memory; Synchronization; Very large scale integration;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.14
