DocumentCode :
3359695
Title :
Diagnostic Test Generation for Arbitrary Faults
Author :
Bhatti, Naresh K. ; Blanton, R. D Shawn
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
fYear :
2006
fDate :
Oct. 2006
Firstpage :
1
Lastpage :
9
Abstract :
It is now generally accepted that the stuck-at fault model is no longer sufficient for many manufacturing test activities. Consequently, diagnostic test pattern generation based solely on distinguishing stuck-at faults is unlikely to achieve the resolution required for emerging fault types. In this work we describe a new diagnostic ATPG implementation that uses a generalized fault model. It can be easily used in any diagnosis framework to refine diagnostic resolution for complex defects. For various types of faults that include, for example, bridge, transition, and transistor stuck-open, we show that diagnostic resolution can be significantly enhanced over a traditional diagnostic test set aimed only at stuck-at faults. Finally, we illustrate the use of our diagnostic ATPG to distinguish faults derived from a state-of-the-art diagnosis flow based on layout
Keywords :
automatic test pattern generation; fault diagnosis; logic testing; arbitrary faults; diagnostic ATPG implementation; diagnostic resolution; diagnostic test generation; generalized fault model; layout based diagnosis flow; stuck-at faults; Automatic test pattern generation; Bridges; Circuit faults; Circuit testing; Computer aided manufacturing; Electronic mail; Fault detection; Fault diagnosis; Test pattern generators; Virtual manufacturing; ATPG; Fault diagnosis; VLSI Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2006. ITC '06. IEEE International
Conference_Location :
Santa Clara, CA
ISSN :
1089-3539
Print_ISBN :
1-4244-0292-1
Electronic_ISBN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2006.297647
Filename :
4079325
Link To Document :
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