Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization

Traditional methods for channel equalization often involve cascading, a pipelined A/D converter and a FIR filter. Given the nature of pipelined converters, a new method is proposed that performs partial equalization within the pipelined A/D thus reducing the number of taps required for the FIR filter. Simulations have shown it is possible to save 54 flip-flops at the cost of -32 dB of NSR error for a typical Ethernet channel equalizer. Further hardware can be saved if more error can be tolerated in an application. The system level design and equations describing the hardware requirements have been provided.