A novel 0.15 /spl mu/m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions

Author

Takagi, M.T. ; Miyashita, K. ; Koyama, H. ; Nakajima, K. ; Miyano, K. ; Akasaka, Y. ; Hiura, Y. ; Inaba, S. ; Azuma, A. ; Koike, H. ; Yoshimura, H. ; Suguro, K. ; Ishiuchi, H.

Author_Institution

ULSI Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

455

Lastpage

458

Abstract

A 0.15 /spl mu/m CMOS technology integrating W/WNx/polysilicon gate electrodes and Ti silicided source/drain diffusions is presented in this paper. Gate electrodes with sheet resistance as low as 1.6 /spl Omega//sq. and Ti silicided source/drain diffusions of 3.6 /spl Omega//sq. are realized. As a result, both the gate RC delay and parasitic source/drain resistance are minimized and high circuit performance is achieved.

Keywords

CMOS integrated circuits; circuit optimisation; delays; diffusion barriers; integrated circuit measurement; integrated circuit metallisation; ion implantation; leakage currents; titanium compounds; tungsten; tungsten compounds; 0.15 mum; CMOS technology; Ti silicided source/drain diffusions; TiSi/sub 2/; W-WN-Si; W/WNx/polysilicon gate electrode; gate RC delay; high circuit performance; high energy ion implantation; low junction leakage current; parasitic source/drain resistance minimization; sheet resistance; Annealing; CMOS technology; Capacitance; Circuit optimization; Degradation; Delay; Electrodes; Leakage current; Silicidation; Silicides;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.553625

Filename

553625