Title :
A scalable digitalized buffer for gigabit I/O
Author :
Lu, Hungwen ; Su, Chauchin ; Liu, Chien-Nan
Author_Institution :
Nat. Central Univ., Jhongli
Abstract :
A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18 mum CMOS process, the I/O occupies an area of 0.014 mm2 and operates from 4 Gbps@1.9 V to 1.5 Gbps@1.1 V.
Keywords :
CMOS integrated circuits; buffer circuits; CMOS process; gigabit I/O; inductive biasing circuit; inverters; scalable digitalized buffer; serial I/O; supply voltage scalability; transmission gates; Bandwidth; Capacitance; Circuit noise; Driver circuits; Feedback circuits; Inverters; Low voltage; RLC circuits; Resistors; Scalability; Buffer; I/O; SSN;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672068
