• DocumentCode
    3359944
  • Title

    Modeling ionizing radiation effects in solid state materials and CMOS devices

  • Author

    Barnaby, H.J. ; Mclain, M.L. ; Esqueda, I.S. ; Chen, X.J.

  • Author_Institution
    Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ
  • fYear
    2008
  • fDate
    21-24 Sept. 2008
  • Firstpage
    273
  • Lastpage
    280
  • Abstract
    A comprehensive model is presented which enables the effects of ionizing radiation on bulk CMOS devices and integrated circuits to be simulated with closed form functions. The model adapts general equations for defect formation in uniform SiO2 films to facilitate analytical calculations of trapped charge and interface trap buildup in structurally irregular and radiation sensitive shallow trench isolation (STI) oxides. A new approach whereby non-uniform defect distributions along the STI sidewall are calculated, integrated into implicit surface potential equations, and ultimately used to model radiation-induced ldquoedgerdquo leakage currents in n-channel MOSFETs is described. The results of the modeling approach are compared to experimental data obtained on 130 nm and 90 nm devices. The features having the greatest impact on the increased radiation tolerance of advanced deep-submicron bulk CMOS technologies are also discussed. These features include increased doping levels along the STI sidewall.
  • Keywords
    CMOS integrated circuits; integrated circuit modelling; isolation technology; radiation hardening (electronics); CMOS devices; MOSFET; advanced deep-submicron bulk CMOS technologies; closed form functions; defect formation; integrated circuits; interface trap buildup; ionizing radiation effects modeling; leakage currents; nonuniform defect distributions; shallow trench isolation oxides; size 130 nm; size 90 nm; solid state materials; CMOS integrated circuits; CMOS technology; Circuit simulation; Equations; Integrated circuit modeling; Ionizing radiation; Leakage current; Semiconductor device modeling; Solid modeling; Solid state circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2018-6
  • Electronic_ISBN
    978-1-4244-2019-3
  • Type

    conf

  • DOI
    10.1109/CICC.2008.4672075
  • Filename
    4672075