DocumentCode
3359946
Title
Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis
Author
Kao, Yu-Long ; Chuang, Wei-Shun ; Li, James C M
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
fYear
2006
fDate
Oct. 2006
Firstpage
1
Lastpage
9
Abstract
A diagnosis technique is presented to locate seven types of single faults in scan chains, including stuck-at faults and timing faults. This technique implements the Jump Simulation, a novel parallel simulation technique, to quickly search for the upper and lower bounds of the fault. Regardless of the scan chain length, Jump Simulation packs multiple simulations into one so the simulation time is short. In addition, Jump Simulation tightens the bounds by observing the primary outputs and scan outputs of good chains, which are ignored by most previous techniques. Experiments on ISCAS´89 benchmark circuits show that, on the average, only three failing patterns are needed to locate faults within ten scan cells. The proposed technique is still very effective when failure data is truncated due to limited ATE memory
Keywords
automatic test pattern generation; fault simulation; logic testing; ATE; ISCAS´89; Jump Simulation; automatic test equipment; failing patterns; parallel simulation; scan chain fault diagnosis; stuck-at faults; timing faults; Automatic test pattern generation; Circuit faults; Circuit simulation; Fault diagnosis; Hardware; Laboratories; Latches; Logic; Production; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2006. ITC '06. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
1-4244-0292-1
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2006.297659
Filename
4079337
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