Analysis of the impact of interfacial oxide thickness variation on metal-gate high-K circuits

In this paper we analyze the impact of interfacial oxide thickness variations on metal-gate high-K circuits. A simulation methodology is developed which considers a holistic model of the interaction of interfacial oxide layer thickness variation with the transistor electrostatic and transport properties. The unique nature of the high-k devices is thus captured and its influence on circuit parameters is investigated. It is shown that, the interfacial oxide thickness variation need to be effectively controlled to reduce circuit variability and fully exploit the advantage of metal gate high-k technologies.