Title :
A 12b 50MSPS 34mW pipelined ADC
Author :
Yu, H. ; Chin, S.W. ; Wong, B.C.
Author_Institution :
Nat. Semicond., Santa Clara, CA
Abstract :
A 12 bit 50 MSPS pipelined ADC is fabricated in 0.18 mum CMOS process. Internal reference buffers without off-chip capacitors are implemented under 1.8 V power supply voltage for 2 Vp-p input signal swing. Opamp sharing and removal of explicit S/H stage are utilized for low power dissipation. Occupying 1.81times0.76 mm2, ADC achieves SNR of 70.4 dBFS, SFDR of 86 dBFS and ENOB of 11.3 b at Fin of 10 MHz. It consumes 34 mW with FOM of 0.27 pJ/Step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; buffer circuits; operational amplifiers; CMOS process; analog-digital converters; internal reference buffers; low power dissipation; opamp sharing; pipelined ADC; power 34 mW; size 0.18 mum; voltage 1.8 V; word length 12 bit; Bandwidth; Calibration; Capacitors; Circuits; Crosstalk; Energy consumption; Linearity; Power dissipation; Signal design; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672080
