• DocumentCode
    3360072
  • Title

    A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process

  • Author

    Singh, Pratap Narayan ; Kumar, Ashish ; Debnath, Chandrajit ; Malik, Rakesh

  • Author_Institution
    STMicroelectronics, Noida
  • fYear
    2008
  • fDate
    21-24 Sept. 2008
  • Firstpage
    305
  • Lastpage
    308
  • Abstract
    This paper describes an 11 b ADC realized using a 2.5 b pipelined stage followed by 9 b time interleaved SAR. Presented ADC designed in 65 nm CMOS process occupies 0.3 mm2 area, achieves 59.1 dB SINAD at 100 Ms/s sampling frequency while dissipating 15 mW power from 1.2 V supply and resulting FOM is 0.20 pJ/step.
  • Keywords
    CMOS digital integrated circuits; analogue-digital conversion; ADC; FOM; SINAD; analogue-digital conversion; digital CMOS; power 15 mW; size 65 nm; time interleaved SAR; voltage 1.2 V; Bandwidth; CMOS process; Capacitors; Differential amplifiers; Driver circuits; Energy consumption; Frequency; MOSFETs; Sampling methods; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2018-6
  • Electronic_ISBN
    978-1-4244-2019-3
  • Type

    conf

  • DOI
    10.1109/CICC.2008.4672082
  • Filename
    4672082
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3360072