• DocumentCode
    3360093
  • Title

    A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS

  • Author

    Cao, Zhiheng ; Yan, Shouli

  • Author_Institution
    Qualcomm, San Diego, CA
  • fYear
    2008
  • fDate
    21-24 Sept. 2008
  • Firstpage
    309
  • Lastpage
    312
  • Abstract
    A 10 b 210 MS/s two-step ADC has been implemented in 0.13 mum digital CMOS with an active area of 0.38 mm2. Using a proposed capacitor network implemented with small value interconnect capacitors which replaces the resistor ladder/multiplexer in conventional sub-ranging ADCs, and proposed offset canceling comparators, it achieves 74 dB SFDR/55 dB SNDR for 10 MHz and 71 dB SFDR/52 dB SNDR for 100 MHz inputs at 210 MS/s while consuming 52 mW from a 1.2 V supply.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; capacitors; receivers; CMOS; analogue-digital conversion; capacitor network; digital-IF receivers; interconnect capacitors; power 52 mW; size 0.13 mum; Circuits; Clocks; Digital filters; Frequency; Linearity; MOS capacitors; Multiplexing; Resistors; Sampling methods; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2018-6
  • Electronic_ISBN
    978-1-4244-2019-3
  • Type

    conf

  • DOI
    10.1109/CICC.2008.4672083
  • Filename
    4672083
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3360093