Yield/cost modeling for electronics wafer fabrication and evaluation of the impact of minimum acceptable die yield criteria on statistical wafer and die yields and costs

Summary form only given. In this paper, a yield/cost model has been derived to link upstream customer-defined specifications and design/technical criteria with electronics wafer fabrication process constraints/capabilities and downstream wafer and die yields and costs for simple electronics transducer wafer fabrication. Additionally, a statistical model has been developed, and when used in conjunction with the yield/cost model, it attempts to diffuse the conflict between engineering and manufacturing and maximize profits through better cost effective decisions by predetermining the impact of the minimum acceptance die yield (MADY) criteria on the statistical wafer and die yields and hence on the wafer and die costs