Characteristics and applications of a 0.6 /spl mu/m bipolar-CMOS-DMOS technology combining VLSI non-volatile memories

Author

Contiero, C. ; Galbiati, P. ; Palmieri, M. ; Vecchi, L.

Author_Institution

Dedicated Products Group, SGS-Thomson Microelectron., Milan, Italy

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

465

Lastpage

468

Abstract

This paper describes the 5th generation, designed at 0.6 /spl mu/m, of the BCD process family commercially introduced ten years ago. Called BCD5, this smart power process provides very dense and high performance bipolar, CMOS and DMOS functions and is compatible with VLSI EPROM, EEPROM and Flash Non-Volatile Memories. Extremely complex systems requiring analog, digital and power functions, /spl mu/P cores and significant amount of memories (hundreds of Kbits) can be realized in one chip (Super Smart Power integration) using BCD5.

Keywords

BIMOS integrated circuits; EPROM; VLSI; integrated circuit technology; integrated memory circuits; power integrated circuits; 0.6 mum; BCD process family; BCD5; EEPROM; VLSI EPROM; VLSI nonvolatile memories; bipolar-CMOS-DMOS technology; extremely complex systems; flash nonvolatile memories; smart power process; super smart power integration; system oriented power technology; CMOS process; CMOS technology; EPROM; Flash memory; Implants; Nonvolatile memory; Plugs; Power integrated circuits; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.553627

Filename

553627