Title :
A Graph-theoretic Approach For One-dimensional Logic Gate Assignment Of Vlsi Circuit Layout
Author :
Wu, Shuxian ; Chan, Shu Park
Author_Institution :
CAS Research Laboratory
Keywords :
Content addressable storage; Laboratories; Logic arrays; Logic circuits; Logic gates; Minimization methods; Testing; Very large scale integration; Wiring;
Conference_Titel :
Signals, Systems and Computers, 1988. Twenty-Second Asilomar Conference on
DOI :
10.1109/ACSSC.1988.754674
