DocumentCode

336020

Title

A Graph-theoretic Approach For One-dimensional Logic Gate Assignment Of Vlsi Circuit Layout

Author

Wu, Shuxian ; Chan, Shu Park

Author_Institution

CAS Research Laboratory

Volume

2

fYear

1988

fDate

1988

Firstpage

872

Lastpage

875

Keywords

Content addressable storage; Laboratories; Logic arrays; Logic circuits; Logic gates; Minimization methods; Testing; Very large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1988. Twenty-Second Asilomar Conference on

ISSN

1058-6393

Type

conf

DOI

10.1109/ACSSC.1988.754674

Filename

754674