Power distribution network co-simulation for cost-effective system design

Author

Hsu, Jimmy ; Lin, Jack ; Chen, Tung-Yang ; Guo, Wei-Da ; Yang, Sam ; Lee, Renee

Author_Institution

Himax Technol., Inc., Taipei, Taiwan

fYear

2009

fDate

2-4 Dec. 2009

Firstpage

1

Lastpage

4

Abstract

The power distribution network (PDN) analysis, including chip, quad-flat-package (QFP) and two-layer board, was presented for the cost-effective system design in the high-speed IO application. The physical interaction between the high-inductive shared off-chip design and capacitive on-chip network was discussed to figure out the related potential issues, such as anti-resonance and the serious interference in PDN. Finally, the integrated analysis with frequency-dependent PDN characteristics, instead of the traditional complicated spice model, was analyzed and validated in the time domain to correlate with the simultaneously switching noise in the frequency domain finding.

Keywords

circuit simulation; electronics packaging; power electronics; capacitive on-chip network; cost-effective system design; frequency domain finding; frequency-dependent PDN characteristics; high-inductive shared off-chip design; high-speed IO application; integrated analysis; power distribution network analysis; power distribution network cosimulation; quad-flat-package; simultaneously switching noise; two-layer board; Bonding; Costs; Electronics packaging; MOS capacitors; Network-on-a-chip; Power systems; Printed circuits; System analysis and design; System-on-a-chip; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Design of Advanced Packaging & Systems Symposium, 2009. (EDAPS 2009). IEEE

Conference_Location

Shatin, Hong Kong

Print_ISBN

978-1-4244-5350-4

Electronic_ISBN

978-1-4244-5351-1

Type

conf

DOI

10.1109/EDAPS.2009.5403995

Filename

5403995