DocumentCode :
3360249
Title :
GPGPU-based Latency Insertion Method: Application to PDN simulations
Author :
Inoue, Yuta ; Sekine, Tadatoshi ; Asai, Hideki
Author_Institution :
Grad. Sch. of Sci. & Technol., Shizuoka Univ., Hamamatsu, Japan
fYear :
2009
fDate :
2-4 Dec. 2009
Firstpage :
1
Lastpage :
4
Abstract :
With the progress of high-density integration technology of the circuits, a variety of signal and power integrity problems have become serious and important for the electronic design. This paper describes the fast circuit simulation by GPGPU-LIM (GPGPU-based Latency Insertion Method). First, LIM is reviewed, which is a fast algorithm. Next, implementation of LIM on the general purpose computing on graphic processing unit (GPGPU) is shown. Furthermore, this method is applied to the simulation of power distribution networks (PDNs). Finally, it is confirmed that GPGPU-based LIM is very practical and efficient for the large-scale PDN simulations.
Keywords :
circuit simulation; computer graphic equipment; distribution networks; power engineering computing; GPGPU; PDN simulations; circuit simulation; general purpose computing on graphic processing unit; latency insertion method; power distribution networks; power integrity; signal integrity; Circuit simulation; Circuit topology; Computational modeling; Delay; Graphics; Kirchhoff´s Law; Large-scale systems; Network topology; Power systems; Signal design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Design of Advanced Packaging & Systems Symposium, 2009. (EDAPS 2009). IEEE
Conference_Location :
Shatin, Hong Kong
Print_ISBN :
978-1-4244-5350-4
Electronic_ISBN :
978-1-4244-5351-1
Type :
conf
DOI :
10.1109/EDAPS.2009.5403996
Filename :
5403996
Link To Document :
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