Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues

Author

Bayraktaroglu, Ismet ; Hunt, Jim ; Watkins, Daniel

Author_Institution

Sun Microsystems, Sunnyvale, CA

fYear

2006

fDate

Oct. 2006

Firstpage

1

Lastpage

7

Abstract

A low cost ATE-based cache resident test methodology is presented in this paper for testing cores of microprocessor chips with non-deterministic main memory access. No non-determinism (ND) or training sequence handling of the SerDes is needed, simplifying test development, reducing the need for expensive next generation ATE that handle SerDes, and simplifying debug as the SerDes are not tested or used. Even low cost testers (LCT) with low speed interface support initially developed for structural test can be enabled to run these tests

Keywords

automatic test equipment; cache storage; integrated circuit testing; microprocessor chips; ATE-based cache resident test methodology; SerDes; cache resident functional microprocessor testing; low cost testers; microprocessor chips; nondeterministic main memory access; training sequence handling; Automatic test pattern generation; Built-in self-test; Cost function; Logic testing; Manufacturing; Microprocessors; Pins; Silicon; Sun; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2006. ITC '06. IEEE International

Conference_Location

Santa Clara, CA

ISSN

1089-3539

Print_ISBN

1-4244-0292-1

Electronic_ISBN

1089-3539

Type

conf

DOI

10.1109/TEST.2006.297675

Filename

4079353