A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

Author

Wei, Ting-Chen ; Liu, Wei-Chang ; Tseng, Chi-Yao ; Long, Syu-Siang ; Jou, Shyh-Jye ; Shiue, Muh-Tian

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu

fYear

2008

fDate

21-24 Sept. 2008

Firstpage

351

Lastpage

354

Abstract

An OFDM baseband receiver chip for DVB-T/H application is proposed in this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200 ppm sampling clock offset (SCO) and plusmn 50 subcarrier spacing carrier frequency offset (CFO) in multipath environment. The total memory requirement of this chip is 102.8 KB and the total equivalent gate count (including memory) is about 806,800 gates. By using 0.18 mum CMOS process, the power consumption is 28 mW at 1.45 V, 40 MHz and core size of this chip is 3600 mum times 3600 mum.

Keywords

CMOS integrated circuits; OFDM modulation; channel estimation; digital video broadcasting; receivers; synchronisation; CMOS process; DVB-T/H; OFDM baseband receiver chip; all-digital jointed detection/synchronization loops; carrier frequency offset; channel estimation; power 28 mW; sampling clock offset; Baseband; CMOS process; Channel estimation; Clocks; Digital video broadcasting; Energy consumption; Frequency estimation; Frequency synchronization; OFDM; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-2018-6

Electronic_ISBN

978-1-4244-2019-3

Type

conf

DOI

10.1109/CICC.2008.4672094

Filename

4672094