Novel I/O-bump design and optimization for chip-package codesign

While the advanced very large scale integration (VLSI) circuit is scaling to deep-submicrometer (DSM) technology, the I/O placement plays a key role in affecting the die size and interconnect. The flip-chip area-array ICs meet the requirements of higher I/O density and lower parasitic effects, but essentially need the optimized I/O and bump placement. In this paper we skip the redistribution layer (RDL) routing and design the specific I/O-bump tiles based on an innovative I/O-row scheme. By considering the package ball location, our proposed I/O-bump planning methodologies produce a package-aware I/O-bump location for chip-level core cell placement and package-level routing task. Thus, our algorithms provide the concurrent chip-package coplanning/codesign flow and dramatically speed up the design process. The experimental results show that our methods optimize the performance metrics in designing the interface between chip and package, such as the net crossing, total wirelength and length deviation.