A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorne

Author

Taufique, Mohammed H. ; Okpisz, Alex ; Ahmed, Haseeb N. ; Riley, John R. ; Hasan, Mohammad M. ; Gerosa, Gian

Author_Institution

Intel Corp., Austin, TX

fYear

2008

fDate

21-24 Sept. 2008

Firstpage

403

Lastpage

406

Abstract

A self-timed, phase based 512KB L2 cache design in 45 nm CMOS process for a low power IA core is presented. The design supports back to back access every core clock by performing sense amplifier (SA) evaluation and SA precharge (SAPCH) in one phase. Dynamic latch is used in the data-out path to enable the use of narrowest SA and latch pulse (LATCK) width during high volume manufacturing (HVM). Power gated (PG) WL driver, sleep and deep sleep for the SRAM array along with floating the bit lines and tri-state write driver schemes are implemented to reduce cache leakage power. The design meets the performance requirement of 2.0 GHz and 1.0 GHz at 1.0 V and 0.75 V respectively at 90C.

Keywords

CMOS digital integrated circuits; cache storage; logic design; microprocessor chips; SRAM array; bit line floating; cache leakage power reduction; high volume manufacturing; latch pulse width; level-2 cache design; low power IA processor Silverthorne; memory size 512 KByte; self-timed cache; sense amplifier evaluation; sense amplifier precharge; size 45 nm; tristate write driver; voltage 0.75 V; voltage 1 V; CMOS process; Circuits; Clocks; Error correction; Latches; Pulse amplifiers; Random access memory; Sleep; Technical Activities Guide -TAG; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-2018-6

Electronic_ISBN

978-1-4244-2019-3

Type

conf

DOI

10.1109/CICC.2008.4672105

Filename

4672105