Title :
A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode
Author :
Kim, Tae-Hyoung ; Liu, Jason ; Kim, Chris H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN
Abstract :
A voltage scalable 0.26 V, 64 kb 8 T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Reverse short channel effect was utilized to improve cell write margin and read performance. A marginal bitline leakage compensation scheme was used during read operation to lower Vmin down to 0.26 V. Floating write bitline and read bitline, auto wordline pulse width control, and a deep sleep mode minimize the active and standby leakage power consumption.
Keywords :
CMOS memory circuits; SRAM chips; CMOS process; SRAM; Vmin lowering technique; auto wordline pulse width control; cell write margin; deep sleep mode; floating write bitline; leakage power consumption; marginal bitline leakage compensation; read bitline; read performance; reverse short channel effect; size 130 nm; storage capacity 64 Kbit; voltage 0.26 V; CMOS process; Circuits; Energy consumption; Leakage current; Logic devices; Low voltage; Random access memory; Space vector pulse width modulation; Turning; USA Councils;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672106
