Clocking circuits for a 16Gb/s memory interface

8 GHz clocking circuits for a 16 Gb/s/pin asymmetric memory interface [1] are described. A combination of an LC-PLL and a ring-PLL achieves improved jitter performance for multiple phase outputs with a wide frequency range. A direct phase mixer and a digitally controlled duty-cycle corrector (DCC) are time-multiplexed between transmitter (TX) and receiver (RX), thereby reducing area and power. The prototype chip implemented in a 65 nm CMOS technology has measured 734 fs RJ (rms) at the TX output when operating at 16 Gb/s.