A 1V 15.6mW 1–2GHz −119dBc/Hz @ 200kHz clock multiplying DLL

A low-phase-noise 1-2 GHz clock multiplier is configurable as PLL or DLL. Starting in PLL-mode, a lock-detect circuit switches the circuit to DLL and simultaneously reconfigures the loop filter. Upon loss of lock the circuit automatically falls back to PLL-mode. The number of stages in the VCO/delay line is programmable to 8-10-12-14-16, implementing band selection with modest tuning gain K_VCO. Multiplication is selectable from 2 to 64. The 0.11 mm² 90 nm CMOS chip also includes charge pump and divider, both programmable. With 80 MHz reference, phase noise is essentially flat and measures -125 dBc/Hz and -119 dBc/Hz @ 200 kHz offset for 0.92 and 1.92 GHz output respectively. Total maximum power consumption is 15.6 mW from a 1 V supply.