• DocumentCode
    3360809
  • Title

    Testing MRAM for Write Disturbance Fault

  • Author

    Su, Chin-Lung ; Tsai, Chih-Wea ; Wu, Cheng-Wen ; Hung, Chien-Chung ; Chen, Young-Shying ; Kao, Ming-Jer

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
  • fYear
    2006
  • fDate
    Oct. 2006
  • Firstpage
    1
  • Lastpage
    9
  • Abstract
    The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. The proposed WDF model is justified by chip measurement results. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. An MRAM chip has been designed and fabricated using a CMOS-based 0.18mum technology. We also present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with March C. Finally, we present a March 17N diagnosis algorithm for identifying the WDF
  • Keywords
    CMOS memory circuits; SPICE; circuit simulation; fault simulation; integrated circuit testing; magnetic storage; magnetic tunnelling; random-access storage; 0.18 micron; CMOS-based technology; EEPROM; MRAM fault simulator; MRAM testing; March 17N diagnosis algorithm; March C; RAM; RAMSES-M; SOC; SPICE macro model; chip measurement; circuit simulation; flash memory; magnetic random access memory; magnetic tunneling junction device; on-chip memories; write disturbance fault; Circuit faults; Circuit simulation; Circuit testing; EPROM; Flash memory; Magnetic field measurement; Magnetic tunneling; Random access memory; Read-write memory; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2006. ITC '06. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    1-4244-0292-1
  • Electronic_ISBN
    1089-3539
  • Type

    conf

  • DOI
    10.1109/TEST.2006.297702
  • Filename
    4079380