Title :
A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links
Author :
Tomkins, A. ; Aroca, R.A. ; Yamamoto, T. ; Nicolson, S.T. ; Doi, Y. ; Voinigescu, S.P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON
Abstract :
This paper presents a 1.2 V 60 GHz zero-IF transceiver fabricated in a 65 nm CMOS process with a digital back-end. The chip includes a receiver with 14.7 dB gain, a low 5.6 dB noise figure, a 60 GHz LO distribution tree, a 64 GHz static frequency divider, and a direct BPSK modulator operating over the 55-65 GHz band at data rates exceeding 3.5 Gb/s. The chip consumes 374 mW (232 mW) from 1.2 V (1.0 V) and occupies 1.28 times 0.81 mm2. The transceiver was characterized over temperature up to 85degC and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on typical and fast process splits. The transceiver performance is demonstrated using a 3.5 Gb/s 2-meter wireless transmit-receive link over the 55-64 GHz range.
Keywords :
CMOS analogue integrated circuits; MIMIC; frequency dividers; low noise amplifiers; phase shift keying; transceivers; BPSK modulator; CMOS process; LO distribution tree; digital back-end; frequency 60 GHz; gain 14.7 dB; low noise amplifier; noise figure 5.6 dB; size 65 nm; static frequency divider; voltage 1.2 V; wireless transmit-receive link; zero-IF transceiver; Binary phase shift keying; CMOS process; Circuits; Frequency conversion; Gain; Manufacturing processes; Noise figure; Power supplies; Temperature; Transceivers;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672123
