DocumentCode
3360897
Title
IEEE P1581 - Getting More Board Test Out of Boundary Scan
Author
Ehrenberg, H.
Author_Institution
GOEPEL Electron., Austin, TX
fYear
2006
fDate
22-27 Oct. 2006
Firstpage
1
Lastpage
10
Abstract
IEEE P1581 has undergone significant improvement since its introduction. This paper explains the choice of simple, low overhead solutions the proposed standard provides in overcoming one of boundary scan´s greatest bottlenecks: test of complex memory devices. Design for testability guidelines are provided to allow board designers and test engineers to take full advantage of this new test technique
Keywords
IEEE standards; boundary scan testing; design for testability; integrated circuit interconnections; integrated memory circuits; IEEE P1581; board test; boundary scan; complex memory devices testing; design for testability; Circuit testing; Clocks; Design engineering; Design for testability; Electronic equipment testing; Guidelines; Pins; Random access memory; Read-write memory; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2006. ITC '06. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
1-4244-0291-3
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2006.297707
Filename
4079385
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