Abstract :
The scaling of CMOS technology is coming soon to an end, and yet it is unclear whether CMOS devices in the 10-20 nanometer range will find a useful place in semiconductor products. At the same time, new silicon-based technologies (e.g., silicon nanowires) and non-silicon based (e.g., carbon nanotubes) show the promise of replacing traditional transistors. Within this rich set of possibilities, hybridization of technologies will be extremely important to achieve specific objectives, such as seamless interfacing to embedded sensors, ultra-low power consumption, wearable systems, etc. In order for the technology to be widely applicable, specific architectures to match the technology. Morever, a new set of design tools and methodologies will be required.
