Modeling and Testing Process Variation in Nanometer CMOS

As device technology progresses toward 45nm and beyond, the fidelity of the process parameter modeling becomes questionable. In this paper we propose the concept of process variation (PV) testing. This is achieved by applying an innovative fault model and test methodology that uses PV sensing circuitry and frequency domain analysis. Rather than pinpointing the variation of different parameters, our architecture looks at the effect of PV in a chip indirectly and collectively. The novelty of this architecture is in shifting the strategy of VLSI testing to frequency domain by using a distributed network of frequency-sensitive circuits such as ring oscillators. This provides an intrinsic advantage by minimizing the effect of noise (signal integrity loss, crosstalk, IR drop, etc.) and by using the powerful concept of digital signal processing for test analysis. The test architecture does not interfere with the rest of the circuit thus providing freedom to tune accuracy of the PV test by choosing the proper number and type of oscillators