Title :
Timing yield enhancement through soft edge flip-flop based design
Author :
Wieckowski, Michael ; Park, Young Min ; Tokunaga, Carlos ; Kim, Dong Woon ; Foo, Zhiyoong ; Sylvester, Dennis ; Blaauw, David
Author_Institution :
Univ. of Michigan, Ann Arbor, MI
Abstract :
The first evaluation of a soft-edge flip-flop is presented as an alternative to useful-skew and latch-based designs for variation compensation in a 16-bit 8-tap FIR filter in 0.13 mum CMOS. An 11.2% performance improvement was achieved over a standard hard edge data flip-flop (9.2% when post-silicon useful-skew is applied).
Keywords :
CMOS integrated circuits; FIR filters; flip-flops; integrated circuit yield; CMOS integrated circuit; FIR filter; latch-based designs; post-silicon useful-skew; size 0.13 mum; soft edge flip-flop; timing yield enhancement; word length 16 bit; Circuits; Clocks; Delay effects; Flip-flops; Latches; Master-slave; Performance analysis; Pipelines; Pulse generation; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672142
