Title :
Low-Gain-Wide-Range 2.4-GHz Phase Locked Loop
Author :
Rahajandraibe, W. ; Zaïd, L. ; De Beaupré, V. Cheynet ; Roche, J.
Author_Institution :
L2MP - Univ. of Provence, Marseille
Abstract :
The feasibility of low noise sensitivity 2.4-GHz Phase Locked Loop for use in wireless communications as well as in clock generation circuit is demonstrated. The system uses low-gain-multi-band Voltage Controlled Oscillator which achieves a phase noise of -98 dBc/Hz @ 1MHz offset while a lock time of 150-¿s has been obtained from the PLL loop. The design has been implemented on standard CMOS technology.
Keywords :
CMOS integrated circuits; UHF circuits; UHF oscillators; phase locked loops; radio networks; voltage-controlled oscillators; clock generation circuit; frequency 1 MHz; frequency 2.4 GHz; low noise sensitivity; low-gain-wide-range phase locked loop; time 150 mus; voltage controlled oscillator; wireless communications; Circuits; Clocks; Frequency conversion; Frequency synthesizers; Jitter; Noise generators; Phase locked loops; Phase noise; Transceivers; Voltage-controlled oscillators; CMOS; Frequency synthesizer; Low gain; Low jitter; Phase Locked Loop; VCO;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4510922
