HW/SW FPGA Architecture for a Flexible Motion Estimation

In this paper, we present a HW/SW implementation of the motion estimation on a FPGA circuit using the Nios II softcore processor. Furthermore, in multimedia processing, it is well-known that the Sum of Absolute Differences (SAD) operation is the most time consuming operation when it is implemented in a software approach. Our implementation takes into account more than one algorithm of motion estimation processing and supports a parallel hardware implementation of the SAD operation. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S60 FPGA circuit. The performances of our design have been tested using the H.263 video encoder.